1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to the generation of shielding wires in integrated circuits.
2. Description of Related Art
Integrated circuits are typically composed of a multitude of circuit components and interconnecting structures and are widely manufactured on semiconductor chips to process signals. Within a multi-layered integrated circuit chip, these circuit components and interconnecting structures can be located on one or more layers of the chip and can be connected to different power and ground networks of the chip.
One interconnecting structure used in integrated circuits is a signal wire. Typically, signal wires are routed on one or more metal layers of an integrated circuit chip. As there are only a limited number of metal layers in each chip, circuit designers attempt to make the most efficient use of the available routing space on a metal layer by maximizing the number of signal wires routed on a metal layer.
During the development of an integrated circuit design, signal wires are conventionally designed to a pre-determined signal wire pitch defined by a specified fabrication process or design parameter. In this instance, the term signal wire pitch refers to a distance between the center lines of two adjacent signal wires.
To aid in maintaining the integrity of a signal carried on a signal wire, shielding wires are often routed to each side of a signal wire to reduce the effects of electrical noise on a signal wire. Conventionally, the shielding wire to one side of a signal wire is assigned to a power network, and the shielding wire to the other side of the signal wire is assigned to a ground network. These assignments are typically made according to the design rules of a given integrated circuit.
If shielding wires are to be included in an integrated circuit design, the signal wire pitch must be large enough to accommodate the placement of the shielding wires. Conventionally, shielding wires are offset a pre-determined shielding wire pitch from the signal wire. In this instance, the term shielding wire pitch refers to a distance between the center lines of a signal wire and an adjacent shielding wire. Additionally, adjacent shielding wires are spaced apart according to design rule spacing parameters.
In some integrated circuit designs, a signal wire can be routed in different directions on the same metal layer of a chip, such as to route around various components. Thus, the signal wire can be routed in vertical and horizontal directions on the same metal layer. Typically, these changes in directions are made using wire jogs. In other integrated circuit designs, design rules can dictate that the signal wires be routed in a single direction on a metal layer. In these other designs, vertical segments of the signal wire can be routed on a metal layer different from the horizontal segments. The vertical and horizontal segments are then interconnected between the metal layers using conductive structures, such as vias.
FIG. 1 illustrates a general diagram of signal wires routed in different directions on the same metal layer of an integrated circuit chip according to the prior art. In FIG. 1, signal wires 116_1 and 116_2 are shown routed on metal layer 110 of an integrated circuit chip and interconnecting circuit components 112 and 114. If shielding wires are to be introduced in the design, the signal wire pitch 118 must be large enough to accommodate placement of the shielding wires.
FIG. 2 illustrates a general diagram of signal wires in which vertical and horizontal segments of the signal wires are routed on different metal layers in an integrated circuit according to the prior art. For example, in FIG. 2, design rules can dictate that signal wires be routed in the horizontal direction on metal layer 202 and in the vertical direction on metal layer 204. As illustrated, horizontal segments of signal wire 218 are routed in the horizontal direction on metal layer 202 and vertical segments of signal wire 218 are routed in the vertical direction on metal layer 204. Thus, to allow for direction changes, signal wire 218 is segmented between layers 202 and 204. Conductive interconnections between layers 202 and 204 (shown as dashed lines), such as vias, provide conductive continuity between the vertical and horizontal segments of the signal wire.
As can be appreciated from the illustrations of FIGS. 1 and 2, introduction of shielding wires to an integrated circuit design can be a complicated process as the routing can be required to be multi-directional on a single metal layer or may traverse several layers. Further, each shielding wire assignment to a power or ground network should be in accordance with the design rules for the particular integrated circuit.
Some prior art techniques attempted to generate shielding wire patterns by tracing the routing of each individual signal wire. The trace pattern is duplicated to each side of the signal wire and used as the shielding wire patterns. As shielding wire patterns are separately generated for each signal wire, duplicate shielding wires can be generated between adjacent signal wires, one for each signal wire.
In instances where adequate space was left between signal wires for the placement of shielding wires, the generation of duplicate shielding wires can fall within the design rules of the integrated circuit design. However, in some instances where adequate space was not left between signal wires, the generation of duplicate shielding wires can fall outside of the design rules, such as when the shielding wires overlap or do not have at least a minimum spacing between shielding wires.
Typically, design rule checking using this process can be performed concurrently with the shielding wire generation or as a separate process, but the design rule check is still separately performed for each separate signal wire. In instances, where duplicate, adjacent shielding wires exist between adjacent signal wires, assignment of one shielding wire to a power network and the other to a ground network can result in a power-ground short. In these situations, the design had to be reworked to correct the design rule violations.
To avoid these problems, other prior art techniques added shielding wires to integrated circuit designs either by custom coding the shielding wire design to a specific implementation or by using a full custom layout. Both of these approaches were time consuming and highly susceptible to errors. Additionally, once developed, the resultant custom software often could not be applied to newly integrated circuit designs or processes without significant effort.
Thus, it would be desirable to have a method and/or device that can rapidly, concurrently, and algorithmically generate a shielding wire topology for metal layers of an integrated circuit design that is design rule correct (DRC). Further, once the shielding wire topology is generated, the method and/or device would determine and assign power and ground nets to the shielding wires. Additionally, the method and/or device would be portable between designs and integrated circuit technologies.